The present invention relates to a technique of reducing noise and noise-induced operational failure in a dynamic circuit that uses MOS transistors.
Recently, in the field of semiconductor integrated circuits, process has been increasingly refined, enabling various advantages, such as high-speed operation, area saving, low power consumption and the like. With refined process, as low power supply voltage is necessary, it concurrently causes problems of noise immunity of a circuit.
Conventionally, a circuit called dynamic circuit has been used as one of the circuits for high-speed operation.
FIG. 15 illustrates an example of a conventional dynamic circuit.
Referring to FIG. 15, a reference numeral 101 denotes a P-type MOS transistor. The gate terminal of the P-type MOS transistor 101 is connected to a clock input terminal 107. When a clock signal CK from the clock input terminal 107 is Low (“Low” represents a ground voltage), a precharge node 112 is charged to High (“High” represents a power supply voltage). Reference numerals 102, 103 and 104 denote N-type MOS transistors. The gate terminals of the N-type MOS transistors 102 to 104 are connected to input terminals 108 and 109 and the clock input terminal 107, respectively, and the N-type MOS transistors 102 and 103 are connected together via an intermediate node 113. An input signal A from the input terminal 108 and an input signal B from the input terminal 109 fall in the Low period of the clock signal CK, and maintain at Low or rise in the High period thereof. A reference numeral 105 denotes an inverter that uses the precharge node 112 as an input, and an inversion output thereof is connected to an output terminal 111. A reference numeral 106 denotes a P-type MOS transistor that is conducted when an output signal from the output terminal 111 is at Low, that is, when the precharge node 112 is at High, and the precharge node 112 is thereby maintained at High. The drivability of the P-type MOS transistor 106 is set lower than those of the N-type MOS transistors 102, 103 and 104. When the N-type MOS transistors 102, 103 and 104 are conducted, the precharge node 112 falls. FIG. 16 illustrates waveforms of signals of the dynamic circuit in FIG. 15.
Hereinafter, operation of the conventional dynamic circuit described above will be described.
First, the clock signal CK falls, the P-type MOS transistor 101 is conducted, and the precharge node 112 rises. Subsequently, when the clock signal CK rises, only when the input signals A and B rise, the ground terminal is conducted from the precharge node 112, and the precharge node 112 falls. The signal of the precharge node 112 is outputted to the output terminal 111 through the inverter 105. As such, the output signal falls in the Low period of the clock signal CK, and AND operation results of the input terminals 108 and 109 are outputted in the High period of the clock signal CK.
FIG. 17 illustrates another example of a conventional dynamic circuit.
The dynamic circuit of FIG. 17 differs from the dynamic circuit of FIG. 15 in that the N-type MOS transistor 104 is not provided. However, the other parts of the two dynamic circuits are same to each other, and the operations thereof are also similar to each other.
For example, as shown in FIG. 15, in the conventional dynamic circuit, when only the input signal A rises while the input signal B maintains at Low in the High period of the clock signal CK, only between the precharge node 112 and the intermediate node 113 is conducted. As such, when no charge is accumulated in the intermediate node 113, the charge in the precharge node 112 is shared to the intermediate node 113. Concurrently, the potential of the precharge node 112 approximately drops to the level of High*{C1/(C1+C2)} from High, where C1 represents the capacitance of the precharge node 112 and C2 represents the capacitance of the intermediate node 113. Thereafter, the charge is supplied from the power supply through the P-type MOS transistor 106, returns the precharge node 112 to High. FIG. 16 shows waveforms of the operations described above.
As such, in the dynamic circuit including the intermediate node 113, noise is generated in some cases in the precharge node 112 depending on the combination of values of the input terminals. Due to the noise, it is possible that the noise immunity of the circuit is decreased or, in the worst case, the circuit can cause operational failure.
In order to solve the conventional problems, there is a method of enhancing the drivability of the P-type MOS transistor 106. In that case, the speed of turning the precharge node 112 into Low by the N-type MOS transistors 102, 103 and 104 is reduced, thereby impeding high-speed operation of the circuit.